3位元全加法器

module fulladder (sum, c_out, a, b, c_in);

wire s1, c1, c2;

output sum;

output c_out;

input a, b, c_in;

xor g1(s1, a, b);

xor g2(sum, s1, c_in);

and g3(c1, a,b);

and g4(c2, s1, c_in) ;

xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);

wire [2:0] c;

output [2:0] sum;

output c_out;

input [2:0] a;

input [2:0] b;

input c_in;

fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;

fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;

fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;

endmodule

module main;

reg [2:0] a;

reg [2:0] b;

wire [2:0] sum;

wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial

begin

  a = 4'b0101;

  b = 4'b0000;

end

always #50 begin

  b=b+1;

  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);

end

initial #2000 $finish;

endmodule

1位元全加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder3_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

                $display(" 0+1+0=01 sum is WRONG!");

              else

                $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+1+1=10 sum is WRONG!");

              else

                $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

                $display(" 1+0+0=01 sum is WRONG!");

              else

                $display(" 1+0+0=01 sum is RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out!= 0 | sum !== 0) 

                $display(" 1+0+1=10 sum is WRONG!");

              else

                $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out!= 0 | sum !== 0) 

                $display(" 1+1+0=10 sum is WRONG!");

              else

                $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

 wire a,b,carry_in;

 reg sum,carry_out;

always @(a  or b or carry_in)

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

always @(a  or b or carry_in)

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule

三位元(2+1)

module top;

wire [2:0] A, B,out;
wire SEL;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A[2]);

system_clock #1600 clock3(A[1]);

system_clock #800 clock34(A[0]);

system_clock #400 clock1(B[2]);

system_clock #200 clock4(B[1]);

system_clock #100 clock5(B[0]);

mux hi (out[2], A[2], B[2], SEL);

mux2 lo (out[1:0], A[1:0], B[1:0], SEL);

endmodule



module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>6500)$stop;

endmodule

三位元多工器

module top;

wire A0,A1,A2,B0,B1,B2,SEL,OUT0,OUT1,OUT2;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A2);

system_clock #1600 clock3(A1);

system_clock #800 clock34(A0);

system_clock #400 clock1(B2);

system_clock #200 clock4(B1);

system_clock #100 clock5(B0);

mux M2(OUT2, A2, B2, SEL);

mux M1(OUT1, A1, B1, SEL);

mux M0(OUT0, A0, B0, SEL);

endmodule



module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule


module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>6500)$stop;

endmodule

2位元多工器

odule top;

system_clock #1600 clock1(A1);

system_clock #800 clock2(A0);

system_clock #400 clock3(SEL);

system_clock #200 clock1(B1);

system_clock #100 clock1(B0);

mux M1(OUT1, A1, B1, SEL);

mux M0(OUT0, SEL, A0, B0 );

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule

真直表

多工器

module top;

system_clock #400 clock1(A);

system_clock #200 clock2(B);

system_clock #100 clock3(SEL);

mux M1(OUT, A, B, SEL);

endmodule


module mux(OUT, A, B, SEL)

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule

Verilog 的兩種主要資料型態

1. 線路 (Nets) : 代表連線，不能儲存內容，代表閘或模組之間的連線，不可以被指定 (assign)。

範例：wire、input、output。

2. 暫存 (Reg) :代表存儲空間，就像暫存器一樣，儲存某值，直到下次被指定 (assign) 為止。

範例：reg、input reg、output reg。(可以用來代表正反器 latch、flip-flop)。

注意：Reg 不可與某個元件連結 (Never connected to something)。

參考網址:http://ccckmit.wikidot.com/ve:basic

F0111904 張庭豪 AND閘 104.09.23