2位元多工器

odule top;

system_clock #1600 clock1(A1);

system_clock #800 clock2(A0);

system_clock #400 clock3(SEL);

system_clock #200 clock1(B1);

system_clock #100 clock1(B0);

mux M1(OUT1, A1, B1, SEL);

mux M0(OUT0, SEL, A0, B0 );

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule