三位元多工器

module top;

wire A0,A1,A2,B0,B1,B2,SEL,OUT0,OUT1,OUT2;

system_clock #6400 clock1(SEL);

system_clock #3200 clock2(A2);

system_clock #1600 clock3(A1);

system_clock #800 clock34(A0);

system_clock #400 clock1(B2);

system_clock #200 clock4(B1);

system_clock #100 clock5(B0);

mux M2(OUT2, A2, B2, SEL);

mux M1(OUT1, A1, B1, SEL);

mux M0(OUT0, A0, B0, SEL);

endmodule



module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule


module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD/2) clk=~clk;

end

always@(posedge clk)

if($time>6500)$stop;

endmodule