1位元全加法器

module test_adder1;

 reg a,b;

 reg carry_in ; 

 wire sum;

 wire carry_out;

 adder3_behavorial A1(carry_out, sum, a, b, carry_in);

 initial 

  begin

    carry_in = 0; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+0+0=00 sum is WRONG!");

              else

                $display(" 0+0+0=00 sum is RIGHT!");

    carry_in = 0; a = 0; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 1) 

               $display(" 0+0+1=01 sum is WRONG!");

              else

               $display(" 0+0+1=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

                $display(" 0+1+0=01 sum is WRONG!");

              else

                $display(" 0+1+0=01 sum is RIGHT!");

    carry_in = 0; a = 1; b = 1; 

    # 100 if ( carry_out != 0 | sum !== 0) 

                $display(" 0+1+1=10 sum is WRONG!");

              else

                $display(" 0+1+1=10 sum is RIGHT!");

    carry_in = 1; a = 0; b = 0; 

    # 100 if ( carry_out != 0 | sum !== 1) 

                $display(" 1+0+0=01 sum is WRONG!");

              else

                $display(" 1+0+0=01 sum is RIGHT!");

    carry_in = 1; a = 0; b = 1; 

    # 100 if ( carry_out!= 0 | sum !== 0) 

                $display(" 1+0+1=10 sum is WRONG!");

              else

                $display(" 1+0+1=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 0; 

    # 100 if ( carry_out!= 0 | sum !== 0) 

                $display(" 1+1+0=10 sum is WRONG!");

              else

                $display(" 1+1+0=10 sum is RIGHT!");

    carry_in = 1; a = 1; b = 1; 

    # 100 if ( carry_out != 1 | sum !== 1) 

               $display(" 1+1+1=11 sum is WRONG!");

              else

               $display(" 1+1+1=11 sum is RIGHT!");

    $finish;

  end

endmodule

module adder1_behavorial (carry_out, sum, a, b, carry_in);

 input a, b, carry_in;

 output carry_out, sum;

 wire a,b,carry_in;

 reg sum,carry_out;

always @(a  or b or carry_in)

  assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(a&b&carry_in)|(~a&~b&carry_in); 

always @(a  or b or carry_in)

  assign carry_out = a&carry_in|a&b|b&carry_in; 

endmodule